`timescale 1ns/1ps

module tb();

// Parameters
parameter CLK_FREQ = 50_000_000;  // 50 MHz
parameter BAUD_RATE = 115200;

// Testbench signals
reg clk;
reg rst_n;
reg rxd;
wire [7:0] dout_data;
wire dout_done;

// Instantiate the UART RX module
uart_rx #(
    .CLK_FREQ(CLK_FREQ),
    .UART_BPS(BAUD_RATE)
) uut (
    .clk(clk),
    .rst_n(rst_n),
    .rxd(rxd),
    .dout_data(dout_data),
    .dout_done(dout_done)
);

// Clock generation
initial begin
    clk = 0;
    forever #10 clk = ~clk;  // 50 MHz clock
end

// Test scenario
initial begin
    // Initialize signals
    rst_n = 0;
    rxd = 1;
    
    // Reset
    #100 rst_n = 1;
    #1000;
    send_byte(8'h35);
    send_byte(8'hAA);
    send_byte(8'h12);
    send_byte(8'h34);
    send_byte(8'h56);

    // End simulation
    #10000 $finish;
end

// Task to send a byte
task send_byte;
    input [7:0] byte_to_send;
    integer i;
    begin
        // Start bit
        rxd = 0;
        #(1000000000/BAUD_RATE);
        for (i = 0; i < 8; i = i + 1) begin
            rxd = byte_to_send[i];
            #(1000000000/BAUD_RATE);
        end
        rxd = 1;
        #(1000000000/BAUD_RATE);
    end
endtask


endmodule